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PE4280
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4280 SPDT switch. The RFC port is connected
through a 75 ? transmission line to J2. Port 1 and
Port 2 are connected through 75 ? transmission
lines to J1 and J3. A through transmission line
connects F connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a four metal layer
FR4 material with a total thickness of 0.062". The
transmission lines were designed using a
coplanar waveguide with ground plane (28 mil
core, 21 mil width, 30 mil gap).
J6 provides a means for controlling DC and digital
inputs to the device. The provided jumpers short
the package pin to ground for logic low. When the
jumper is removed, the pin is pulled up to V DD for
logic high.
When the jumper is in place, 3 μA of current will
flow through the 1 M ? pull up resistor. This extra
current should not be attributed to the
requirements of the device.
Proper PCB design is essential for full isolation
performance. This eval board demonstrates good
trace and ground management for minimum
coupling and radiation.
Figure 4. Evaluation Board Layouts
Peregrine Specification 101/0148~03A
Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0195~02A
J6
HEADER 7X2
C1
DNI
R1
1M
C2
DNI
R2
1M
C3
DNI
1
3
5
7
9
11
13
VDD
GND
VSS/GND
GND
C1
GND
C2
GND
GND
GND
GND
GND
GND
GND
2
4
6
8
10
12
14
1
GND
GND
15
J1
1
75 OHM T-Line
2
3
GND
RF1
U1
PE4280
GND
RF2
14
13
75 OHM T-Line
1
J3
J2
75 OHM T-Line
4
5
21
GND
GND
GND
GND
GND
12
11
1
J4
1
75 OHM T-Line
1
J5
?2010-11 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0164-05
│ UltraCMOS? RFIC Solutions
Page 4 of 8
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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